The present invention relates to a signal transmission system effectively applicable to a system LSI, for example.
Recently, to enhance the performance of a system LSI, the index of parallelism, not the clock frequency, of the LSI is increased more and more often. For example, in handling multimedia-related data (i.e., audiovisual data including pictures or music), multiple circuits may be laid out in parallel with each other and coupled to a bus with an increased width, thereby processing the data in parallel and increasing the substantial computation rate. The bus width may also be increased to compensate for the low operating speed of a memory (e.g., a built-in DRAM) for storing the data thereon and thereby increase the effective data transfer rate. For that purpose, a data bus with as broad a width as 4096 bits is sometimes used. However, when data is transferred from a certain block to another by way of a bus of such a broad width, a huge quantity of power is dissipated on the signal lines included in the bus (which will be herein referred to as xe2x80x9cbus linesxe2x80x9d).
Hereinafter, it will be estimated with reference to FIGS. 16 through 18 how much power is dissipated on an 8-bit bus.
FIG. 16 schematically illustrates stray capacitances Ch and Cv, associated with bus lines for a known signal transmission system, as a cross section of a semiconductor substrate. In the illustrated example, an 8-bit bus is made up of eight bus lines B[7] through B[0] that are equally spaced apart from each other horizontally. As shown in FIG. 16, two ground lines GND are laid out on the right- and left-hand sides of the bus lines B[0] and B[7], respectively, and are also equally spaced apart horizontally therefrom. The space S between two adjacent ones of the bus lines B[7] through B[0] is supposed to be equal to the space S between the ground line GND and the bus line B[7] or B[0]. Furthermore, in the example illustrated in FIG. 16, these bus lines B[7] through B[0] and ground lines GND have a thickness T1 and are vertically spaced apart from their underlying structure (which may be either substrate or lower-level interconnect but which is shown as GND in the example illustrated in FIG. 16) by a distance T2. The distance T2 is actually equal to the thickness of an interlevel film existing between the bus lines B[7] through B[0] or ground lines GND and the underlying structure. The bus lines B[7] through B[0] and ground lines GND with a width L are arranged at regular pitches P and are horizontally spaced apart from each other by the space S. For example, T1=T2=1,000 nm, P=1.0 xcexcm, L=0.26 xcexcm and S=0.74 xcexcm. According to the 0.18 xcexcm design rule, the line space S can be decreased down to about 0.2 xcexcm. In the illustrated example, however, the line space S is intentionally increased more than threefold to 0.74 xcexcm to minimize the stray capacitance Ch between two adjacent bus lines. In FIG. 16, Ch denotes a horizontal stray capacitance created between a given bus line and a horizontally adjacent bus or ground line, while Cv denotes a vertical stray capacitance created between a given bus line and the underlying structure.
If the capacitance associated with a line of a length of 4 mm is calculated by a boundary element method, the capacitance associated with the line per unit length (e.g., 1 mm) will be: Ch=0.090 pF/mm and Cv=0.025 pF/mm. Accordingly, even if the line space S is more than three times as long as the minimum value thereof, the horizontal components (i.e., 2xc3x97Ch, because two horizontal stray capacitances Ch exist on right- and left-hand sides of each bus line) account for almost all (i.e., 88% in this example) of the total capacitance (i.e., 2xc3x97Ch+Cv including the vertical component).
Next, it will be described with reference to FIGS. 17 and 18 how charges are stored on each stray capacitance where 8-bit data words xe2x80x9cAAxe2x80x9d and xe2x80x9c55xe2x80x9d (which are both hexadecimal representations) are alternately transferred through the bus lines B[7] through B[0]. In each of these patterns (or data words), every adjacent pair of bits has mutually opposite values (i.e., xe2x80x9c01xe2x80x9d or xe2x80x9c10xe2x80x9d). Also, the respective bits making up the pattern xe2x80x9cAAxe2x80x9d are inverse of the counterparts making up the other pattern xe2x80x9c55xe2x80x9d. Specifically, FIG. 17 illustrates how charges are stored during the transmission of the data pattern xe2x80x9cAAxe2x80x9d, while FIG. 18 illustrates how charges are stored during the transmission of the data pattern xe2x80x9c55xe2x80x9d.
In the example illustrated in FIG. 17 for the data pattern xe2x80x9cAAxe2x80x9d, two adjacent charges stored on each horizontal capacitance Ch have mutually opposite polarities. However, no charges have been stored on the capacitance Ch between the bus line B[0], representing the least significant bit (LSB), and the ground GND on the right-hand side of the bus line B[0] because these lines are at the same potential level. In FIG. 17, voltages are applied so that the two lines, adjacent to the rightmost and leftmost ones of the eight bus lines B[7] through B[0], and the underlying structure are grounded, and the charges stored have all been supplied from bus drivers. Over the respective bus lines B[7] through B[0], shown are the quantities Q1 and Q2 of charges that were supplied from a power supply when the previous data pattern xe2x80x9c55xe2x80x9d was replaced with this data pattern xe2x80x9cAAxe2x80x9d. Q1 represents the quantity of charges stored in a capacitance between two adjacent bus lines and Q2 represents the quantity of charges stored elsewhere as will be described in detail later. As for the vertical capacitances Cv on the other hand, charges have been stored, first, on the capacitance Cv associated with the bus line B[7] representing the most significant bit (MSB), and then on every other bit basis. That is to say, in the example illustrated in FIG. 17, the charges have been stored on only the xe2x80x9c1xe2x80x9d bits of the data pattern xe2x80x9cAAxe2x80x9d.
Suppose the data to be transferred has changed from the pattern xe2x80x9cAAxe2x80x9d shown in FIG. 17 into the pattern xe2x80x9c55xe2x80x9d shown in FIG. 18. In that case, each of the charges stored on every horizontal capacitance Ch between two adjacent bus lines has the same absolute value but the opposite polarity compared to the situation shown in FIG. 17. However, the horizontal capacitance Ch between the leftmost bus line B[7] and the ground GND and the vertical capacitance Cv between the bus line B[7] and the ground GND have been discharged to lose the charges. On the other hand, the horizontal capacitance Ch between the rightmost bus line B[0] and the ground GND and the vertical capacitance Cv between the bus line B[0] and the ground GND have been charged with a current supplied from the bus driver to gain the charges. It should be noted that any capacitance is dischargeable with no current supplied from the power supply.
The charges are stored in this manner for the respective data patterns. Next, it will be described how much charging current flows from the power supply. It should be noted that the supply voltage is supposed to be 1 V for the sake of simplicity.
First, the quantity Q1 of charges stored on each capacitance Ch between two adjacent bus lines where the patterns xe2x80x9cAAxe2x80x9d and xe2x80x9c55xe2x80x9d are transmitted alternately will be considered. For example, on the horizontal capacitance Ch between the two adjacent bus lines B[7] and B[6], a charge quantity Chxc3x971 V (with positive charges located on the right-hand side) is stored during the transmission of the pattern xe2x80x9c55xe2x80x9d as shown in FIG. 18, while a charge quantity Chxc3x971 V (with positive charges located on the left-hand side) is stored during the transmission of the pattern xe2x80x9cAAxe2x80x9d as shown in FIG. 17. To change the charge quantities this way, the bus driver should supply charges in a quantity of 2xc3x97Chxc3x971 V to the bus line B[7] before a pair of these complementary patterns is transmitted once successfully. The second leftmost bus line B[6] is sandwiched between the bus lines B[7] and B[5] that change their logical states alternately. Accordingly, the bus line B[6] should be supplied with twice the quantity of charges. Consequently, the total quantity of charges supplied from the power supply to the capacitances Ch between the adjacent bus lines while those two patterns are transmitted once (i.e., during two data transfer cycles) is {(8xe2x88x921)xc3x97(2xc3x972Ch)}xc3x971 V.
Next, the quantity Q2 of charges stored elsewhere (i.e., not between two adjacent bus lines) where the pattern transmitted changes from xe2x80x9cAAxe2x80x9d into xe2x80x9c55xe2x80x9d, or vice versa, will be described. As for the bus line B[7], for example, a voltage of 0 V is applied to, and a charge quantity of 0 is stored on, the vertical capacitance Cv during the transmission of the pattern xe2x80x9c55xe2x80x9d as shown in FIG. 18. On the other hand, during the transmission of the pattern xe2x80x9cAAxe2x80x9d as shown in FIG. 17, a voltage of 1 V is applied to, and a charge quantity of Cv is stored on, the vertical capacitance Cv thereof. Regarding this bus line B[7], a voltage of 0 V is applied to, and a charge quantity of 0 is stored on, the horizontal capacitance Ch between this line B[7] and the ground GND during the transmission of the pattern xe2x80x9c55xe2x80x9d as shown in FIG. 18. On the other hand, during the transmission of the pattern xe2x80x9cAAxe2x80x9d as shown in FIG. 17, a voltage of 1 V is applied to, and a charge quantity of Ch is stored on, the horizontal capacitance Ch thereof. That is to say, as for the bus line B[7], a charge quantity (Cv+Ch)xc3x971 V is supplied from the power supply to, and then discharged from, the capacitance created elsewhere (or not between the bus lines) while the data patterns transmitted make one round in the order of xe2x80x9cAAxe2x80x9dxe2x86x92xe2x80x9c55xe2x80x9dxe2x86x92xe2x80x9cAAxe2x80x9d. The same statement is applicable to the vertical capacitance Cv associated with any other bus line and to the horizontal capacitance Ch between the rightmost bus line B[0] and the ground GND, because one of the two electrodes of the capacitance Cv or Ch has a fixed potential level. Consequently, the total quantity of charges supplied from the power supply while the data patterns transmitted make one round (i.e., during two data transfer cycles) is (8xc3x97Cv+2Ch)xc3x971 V.
The foregoing example relates to a bus with a width of 8 bits. But the amount of current dissipated from, or charged to, bus lines where two alternating data patterns are transmitted is generalized with respect to a bit width N (which is an integer equal to or greater than 3) as follows:
Current dissipated from bus lines
={Nxc3x97Cv/2+Ch+(Nxe2x88x921)xc3x972xc3x97Ch}xc3x97VDDxc3x971/T
≈(Nxc3x97Cv/2+Nxc3x972Ch)xc3x97VDDxc3x971/Txe2x80x83xe2x80x83(1)
where T is the signal transfer period and VDD is the voltage of a positive power supply. In Equation (1), Nxc3x97Cv/2+Ch is a term representing a capacitance associated with the electrode with a fixed potential, (Nxe2x88x921)xc3x972xc3x97Ch is a term representing a capacitance between two adjacent bus lines, Nxc3x97Cv/2 represents the total vertical capacitance and Nxc3x972Ch represents the total horizontal capacitance.
Suppose an N-bit bus should have its capacitances estimated and simulated. In that case, it is normally unknown what types of lines are adjacent to the bus lines or when the lines are activated or deactivated. Accordingly, the capacitance associated with one of those adjacent lines (i.e., 2xc3x97Ch in the foregoing example) is estimated as a relative capacitance determined with respect to GND. According to this approach,
Current dissipated from bus lines
={Nxc3x97(Cv+2Ch)/2}xc3x97VDDxc3x971/T
=(Nxc3x97Cv/2+Nxc3x97Ch)xc3x97VDDxc3x971/Txe2x80x83xe2x80x83(2)
where Nxc3x97(Cv+2Ch)/2 is a term representing a capacitance associated with the electrode with a fixed potential, Nxc3x97Cv/2 represents the total vertical capacitance and Nxc3x97Ch represents the total horizontal capacitance. Thus, it can be seen that the horizontal capacitance Ch contributes in Equation (1) almost twice as greatly as in Equation (2).
That is to say, a bus line, adjacent to a given bus line, cannot be regarded as an electrode with a fixed potential. Rather it is determined, depending on how the potential level on the adjacent bus line changes relative to the given bus line, how much load capacitance the adjacent bus line constitutes. In the foregoing example where the patterns xe2x80x9cAAxe2x80x9d and xe2x80x9c55xe2x80x9d are transmitted alternately, the potential levels on the adjacent and given bus lines change in mutually opposite phases. Accordingly, the horizontal capacitance Ch looks as if the capacitance constituted twice-greater load capacitance. Also, where the adjacent line is an electrode with a fixed potential (e.g., between the bus line B[7] representing the MSB and GND), the horizontal capacitance Ch looks like 1x load capacitance. Furthermore, although not described in detail, where the potential levels on the given and adjacent bus lines change in phase, the horizontal capacitance Ch looks like 0x load capacitance.
Thus, it can be seen that the power dissipated from bus lines increases proportionally to the bit width N. It can also be seen that the greater the number of bit pairs each changing into mutually opposite values, the greater the power dissipated.
A technique applicable to a signal transmission system for transmitting a signal at a high rate through a bus is disclosed in Japanese Laid-Open Publication No. 9-244776. According to the technique, a signal can be transmitted with its amplitude decreased by preventing any signal potential from increasing excessively due to the existence of a coupling capacitance (i.e., stray capacitance) between adjacent bus lines. This technique supposes that a bus line should be driven by a driver circuit after having been precharged to a predetermined level. For that purpose, an equalizing MOS transistor is interposed between adjacent bus lines. The equalizing MOS transistor is turned on during a precharge interval to shortcircuit the adjacent bus lines together. That is to say, to prevent any signal potential from increasing too much due to the existence of the stray capacitance, the bus lines are precharged to VDD/2 (where VDD is the supply voltage) and then the potentials on the lines are equalized supplementally. However, if VDD is as low as 1.6 V or less, then VDD/2 is 0.8 V or less, which is very close to the threshold voltage of the transistor. But it is difficult to make a power supply that can supply that low voltage of VDD/2 while maintaining sufficient ability thereof.
It is therefore an object of the present invention to reduce the power dissipated from bus lines in a signal transmission system.
To achieve this object, a signal transmission system according to the present invention includes: driver circuit on the transmitting end; receiver circuit on the receiving end; three or more bus lines interposed between the driver and receiver circuits; and equalizer circuit. The equalizer circuit equalizes potential levels on the bus lines with each other while the bus lines are electrically disconnected from a power supply before a signal is transmitted by way of the bus lines. Every time a system with such a configuration transmits a signal, the system can remove the charges that have been stored on a stray capacitance between adjacent bus lines without dissipating power, and can also recycle the charges stored. As a result, the power dissipated from the bus lines can be reduced considerably.
Another signal transmission system according to the present invention includes: driver circuit on the transmitting end; receiver circuit on the receiving end; three or more bus lines interposed between the driver and receiver circuits; and reset circuit. The reset circuit resets potential levels on the bus lines to a low level before a signal is transmitted by way of the bus lines. Every time a system with such a configuration transmits a signal, the system can remove the charges that have been stored on a stray capacitance between adjacent bus lines without dissipating power. As a result, the power dissipated from the bus lines can be reduced.
A third signal transmission system according to the present invention includes: driver circuit on the transmitting end; receiver circuit on the receiving end; and three or more bus lines interposed between the driver and receiver circuits. In this system, the bus lines are so arranged as to reduce the number of adjacent bit pairs, each changing into mutually opposite values at a time. Thus, the power dissipated from the bus lines can be reduced.